Messages in this thread | | | From | Florian Fainelli <> | Subject | Re: arm-smmu 5000000.iommu: Cannot accommodate DMA offset for IOMMU page tables | Date | Sun, 11 Oct 2020 14:59:02 -0700 |
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+Abhimanyu, Ioana, Fabio
On 10/11/2020 1:36 PM, Jim Quinlan wrote: > On Sat, Oct 10, 2020 at 2:53 PM Stephen Rothwell <sfr@canb.auug.org.au> wrote: >> >> Hi Naresh, >> >> Just adding Christoph and Jim to cc] >> >> On Fri, 9 Oct 2020 19:26:24 +0530 Naresh Kamboju <naresh.kamboju@linaro.org> wrote: >>> >>> On Fri, 9 Oct 2020 at 19:24, Naresh Kamboju <naresh.kamboju@linaro.org> wrote: >>>> >>>> >>>> >>>> On Thu, 24 Sep 2020 at 15:26, Joerg Roedel <joro@8bytes.org> wrote: >>>>> >>>>> On Thu, Sep 24, 2020 at 10:36:47AM +0100, Robin Murphy wrote: >>>>>> Yes, the issue was introduced by one of the changes in "dma-mapping: >>>>>> introduce DMA range map, supplanting dma_pfn_offset", so it only existed in >>>>>> the dma-mapping/for-next branch anyway. >>>> >>> >>> FYI, >>> The reported problem still exists on 5.9.0-rc8-next-20201009. >>> >>> [ 1.843814] Driver must set ecc.strength when using hardware ECC >>> [ 1.849847] WARNING: CPU: 4 PID: 1 at >>> drivers/mtd/nand/raw/nand_base.c:5687 nand_scan_with_ids+0x1450/0x1470 >>> [ 1.859676] Modules linked in: >>> [ 1.862730] CPU: 4 PID: 1 Comm: swapper/0 Not tainted >>> 5.9.0-rc8-next-20201009 #1 >>> [ 1.870125] Hardware name: Freescale Layerscape 2088A RDB Board (DT) >>> [ 1.876478] pstate: 40000005 (nZcv daif -PAN -UAO -TCO BTYPE=--) >>> [ 1.882483] pc : nand_scan_with_ids+0x1450/0x1470 >>> [ 1.887183] lr : nand_scan_with_ids+0x1450/0x1470 > > Hi, > > I'm having a hard time coming up with a theory regarding how a commit > concerning DMA offsets can affect the operation of a NAND driver that > appears not to use DMA or the dma-ranges property. Does anyone else > have some ideas, or is there perhaps someone familiar with this test > configuration that I can correspond with to get to the bottom of the > warning?
I believe you are given only a partial warning and just a glimpse of the thread here which is why understanding the connection to the dma ranges parsing is not clear. The start of the thread can be found here:
https://lore.kernel.org/lkml/CA+G9fYvuq58q+GsWnzni0sKSHbubuQz-UaK3TASX26V_a7yBVw@mail.gmail.com/
Robin indicated that the IOMMU probe failure was fixed with:
https://lore.kernel.org/linux-iommu/daedc9364a19dc07487e4d07b8768b1e5934abd4.1600700881.git.robin.murphy@arm.com/T/#u
which is confirmed with the new log from Naresh:
https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20201009/testrun/3284876/suite/linux-log-parser/test/check-kernel-warning-92014/log
however the NAND warning still remains. Someone else familiar with these NXP development boards should fix the DTS so as to provide the require ECC strength property. -- Florian
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