Messages in this thread | | | Subject | Re: [PATCH 3/3] x86/tsc_msr: Make MSR derived TSC frequency more accurate | From | Hans de Goede <> | Date | Thu, 30 Jan 2020 16:56:42 +0100 |
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HI,
On 30-01-2020 16:21, David Laight wrote: > From: Peter Zijlstra >> Sent: 30 January 2020 13:43 > ... >>> + * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: >>> + * 000: 100 * 5 / 6 = 83.3333 MHz >>> + * 001: 100 * 1 / 1 = 100.0000 MHz >>> + * 010: 100 * 4 / 3 = 133.3333 MHz >>> + * 011: 100 * 7 / 6 = 116.6667 MHz >>> + * 100: 100 * 4 / 5 = 80.0000 MHz >> >>> + * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: >>> + * 0000: 100 * 5 / 6 = 83.3333 MHz >>> + * 0001: 100 * 1 / 1 = 100.0000 MHz >>> + * 0010: 100 * 4 / 3 = 133.3333 MHz >>> + * 0011: 100 * 7 / 6 = 116.6667 MHz >>> + * 0100: 100 * 4 / 5 = 80.0000 MHz >>> + * 0101: 100 * 14 / 15 = 93.3333 MHz >>> + * 0110: 100 * 9 / 10 = 90.0000 MHz >>> + * 0111: 100 * 8 / 9 = 88.8889 MHz >>> + * 1000: 100 * 7 / 8 = 87.5000 MHz >> >>> + * Merriefield (BYT MID) SDM MSR_FSB_FREQ frequencies simplified PLL model: >>> + * 0001: 100 * 1 / 1 = 100.0000 MHz >>> + * 0010: 100 * 4 / 3 = 133.3333 MHz >> >>> + * Moorefield (CHT MID) SDM MSR_FSB_FREQ frequencies simplified PLL model: >>> + * 0000: 100 * 5 / 6 = 83.3333 MHz >>> + * 0001: 100 * 1 / 1 = 100.0000 MHz >>> + * 0010: 100 * 4 / 3 = 133.3333 MHz >>> + * 0011: 100 * 1 / 1 = 100.0000 MHz >> >> Unless I'm going cross-eyed, that's 4 times the exact same table. > > Apart from the very last line which duplicates 100MHz. > And the fact that some entries are missing (presumed invalid?) > for certain cpu. > > If the tables are ever used for setting the frequency > then the valid range (and values?) would need to be known. > > I did wonder if the 'mask' was necessary? > Are the unused bits reserved and zero?
They are reserved without having a defined value, the appear to usually be 0 but I would rather not depend on that.
Regards,
Hans
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