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    Subject[PATCH AUTOSEL 5.4 004/107] dt-bindings: reset: meson8b: fix duplicate reset IDs
    Date
    From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

    [ Upstream commit 4881873f4cc1460f63d85fa81363d56be328ccdc ]

    According to the public S805 datasheet the RESET2 register uses the
    following bits for the PIC_DC, PSC and NAND reset lines:
    - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
    - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
    - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)

    Update the reset IDs of these three reset lines so they don't conflict
    with PIC_DC and map to the actual hardware reset lines.

    Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
    Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
    Signed-off-by: Kevin Hilman <khilman@baylibre.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    include/dt-bindings/reset/amlogic,meson8b-reset.h | 6 +++---
    1 file changed, 3 insertions(+), 3 deletions(-)

    diff --git a/include/dt-bindings/reset/amlogic,meson8b-reset.h b/include/dt-bindings/reset/amlogic,meson8b-reset.h
    index c614438bcbdb8..fbc524a900da1 100644
    --- a/include/dt-bindings/reset/amlogic,meson8b-reset.h
    +++ b/include/dt-bindings/reset/amlogic,meson8b-reset.h
    @@ -46,9 +46,9 @@
    #define RESET_VD_RMEM 64
    #define RESET_AUDIN 65
    #define RESET_DBLK 66
    -#define RESET_PIC_DC 66
    -#define RESET_PSC 66
    -#define RESET_NAND 66
    +#define RESET_PIC_DC 67
    +#define RESET_PSC 68
    +#define RESET_NAND 69
    #define RESET_GE2D 70
    #define RESET_PARSER_REG 71
    #define RESET_PARSER_FETCH 72
    --
    2.20.1
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