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SubjectRe: [PATCH 05/16] bus: mhi: core: Add support for ringing channel/event ring doorbells
On Thu, Jan 23, 2020 at 01:44:32PM +0100, Arnd Bergmann wrote:
> On Thu, Jan 23, 2020 at 1:01 PM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > On Thu, Jan 23, 2020 at 12:39:06PM +0100, Arnd Bergmann wrote:
> > > On Thu, Jan 23, 2020 at 12:19 PM Manivannan Sadhasivam
> > > <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > > +int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
> > > > + void __iomem *base, u32 offset, u32 *out)
> > > > +{
> > > > + u32 tmp = readl_relaxed(base + offset);
> > > ....
> > > > +void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
> > > > + u32 offset, u32 val)
> > > > +{
> > > > + writel_relaxed(val, base + offset);
> > >
> > > Please avoid using _relaxed accessors by default, and use the regular
> > > ones instead. There are a number of things that can go wrong with
> > > the relaxed version, so ideally each caller should have a comment
> > > explaining why this instance is safe without the barriers and why it
> > > matters to not have it.
> > >
> > > If there are performance critical callers of mhi_read_reg/mhi_write_reg,
> > > you could add mhi_read_reg_relaxed/mhi_write_reg_relaxed for those
> > > and apply the same rules there.
> > >
> > > Usually most mmio accesses are only needed for reconfiguration or
> > > other slow paths.
> > >
> >
> > Fair point. I'll defer to readl/writel APIs and I also need to add
> > le32_to_cpu/cpu_to_le32 to them.
>
> What do you need the byteswap for? All of the above already
> assume that the registers are little-endian.
>

I thought the readl/writel are native endian... Now I read the macro
definitions once again and looks like these APIs are LE for all archs...
So it is not needed. Sorry for the confusion.

Thanks,
Mani

> Arnd

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