Messages in this thread Patch in this message | | | Date | Wed, 22 Jan 2020 20:04:05 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH v12] x86/split_lock: Enable split lock detection by kernel |
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On Wed, Jan 22, 2020 at 10:55:14AM -0800, Luck, Tony wrote: > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index e9b62498fe75..c3edd2bba184 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -220,6 +220,7 @@ > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > +#define X86_FEATURE_SPLIT_LOCK_DETECT ( 7*32+31) /* #AC for split lock */
That word is already full in tip:
... #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
use word 11 instead.
> +#define MSR_TEST_CTRL 0x00000033 > +#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 > +#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) > + > #define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ > #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ > #define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ > @@ -70,6 +74,10 @@ > */ > #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) > > +#define MSR_IA32_CORE_CAPABILITIES 0x000000cf > +#define MSR_IA32_CORE_CAPABILITIES_SPLIT_LOCK_DETECT_BIT 5 > +#define MSR_IA32_CORE_CAPABILITIES_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPABILITIES_SPLIT_LOCK_DETECT_BIT)
Any chance making those shorter?
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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