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    Subject[PATCH AUTOSEL 4.19 627/671] clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
    Date
    From: Marian Mihailescu <mihailescu2m@gmail.com>

    [ Upstream commit e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1 ]

    Save and restore top PLL related configuration registers for big (APLL)
    and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
    were reset to default values after suspend/resume cycle and performance
    after system resume was affected when performance governor has been selected.

    Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")
    Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
    Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/samsung/clk-exynos5420.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
    index d5af93721299..6473af8903c5 100644
    --- a/drivers/clk/samsung/clk-exynos5420.c
    +++ b/drivers/clk/samsung/clk-exynos5420.c
    @@ -171,6 +171,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
    GATE_BUS_CPU,
    GATE_SCLK_CPU,
    CLKOUT_CMU_CPU,
    + APLL_CON0,
    + KPLL_CON0,
    CPLL_CON0,
    DPLL_CON0,
    EPLL_CON0,
    --
    2.20.1
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