Messages in this thread | | | From | Miquel Raynal <> | Subject | Re: [PATCH v3 3/5] dt-bindings: mtd: denali_dt: document reset property | Date | Tue, 14 Jan 2020 18:06:07 +0100 |
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On Fri, 2019-12-20 at 11:31:53 UTC, Masahiro Yamada wrote: > According to the Denali NAND Flash Memory Controller User's Guide, > this IP has two reset signals. > > rst_n: reset most of FFs in the controller core > reg_rst_n: reset all FFs in the register interface, and in the > initialization sequencer > > This commit specifies these reset signals. > > It is possible to control them separately from the IP point of view > although they might be often tied up together in actual SoC integration. > > At least for the upstream platforms, Altera/Intel SOCFPGA and Socionext > UniPhier, the reset controller seems to provide only 1-bit control for > the NAND controller. If it is the case, the resets property should > reference to the same phandles for "nand" and "reg" resets, like this: > > resets = <&nand_rst>, <&nand_rst>; > reset-names = "nand", "reg"; > > Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> > Acked-by: Rob Herring <robh@kernel.org>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
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