Messages in this thread Patch in this message | | | From | Ong Boon Leong <> | Subject | [PATCH net 4/7] net: stmmac: Fix priority steering for tx/rx queue >3 | Date | Tue, 14 Jan 2020 10:01:13 +0800 |
| |
From: Voon Weifeng <weifeng.voon@intel.com>
Fix MACRO function define for TX and RX user priority queue steering for register masking and shifting.
Fixes: a8f5102af2a7 ("net: stmmac: TX and RX queue priority configuration")
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h index 2dc70d1..798a53a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -97,12 +97,14 @@ #define GMAC_RX_FLOW_CTRL_RFE BIT(0) /* RX Queues Priorities */ -#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) -#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8) +#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + (((x) % 4) * 8), \ + 0 + (((x) % 4) * 8)) +#define GMAC_RXQCTRL_PSRQX_SHIFT(x) (((x) % 4) * 8) /* TX Queues Priorities */ -#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8)) -#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8) +#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + (((x) % 4) * 8), \ + 0 + (((x) % 4) * 8)) +#define GMAC_TXQCTRL_PSTQX_SHIFT(x) (((x) % 4) * 8) /* MAC Flow Control TX */ #define GMAC_TX_FLOW_CTRL_TFE BIT(1) -- 2.7.4
| |