Messages in this thread Patch in this message | | | Date | Sun, 12 Jan 2020 10:40:48 +0800 | From | Shawn Guo <> | Subject | Re: [PATCH 3/3] clk: imx: imx8m: use imx_clk_hw_pll14xx_flags for dram pll |
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On Mon, Dec 30, 2019 at 09:13:10AM +0000, Peng Fan wrote: > From: Peng Fan <peng.fan@nxp.com> > > Use imx_clk_hw_pll14xx_flags for dram pll. > Modify imx_1443x_dram_pll to imx_1443x_dram_readonly, because dram pll > is not expected to be modified from Linux. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/clk-imx8mm.c | 2 +- > drivers/clk/imx/clk-imx8mn.c | 2 +- > drivers/clk/imx/clk-pll14xx.c | 3 +-- > drivers/clk/imx/clk.h | 2 +- > 4 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c > index 2ed93fc25087..55862652b19f 100644 > --- a/drivers/clk/imx/clk-imx8mm.c > +++ b/drivers/clk/imx/clk-imx8mm.c > @@ -337,7 +337,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) > hws[IMX8MM_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); > hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); > hws[IMX8MM_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); > - hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); > + hws[IMX8MM_DRAM_PLL] = imx_clk_hw_pll14xx_flags("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll_readonly, CLK_GET_RATE_NOCACHE); > hws[IMX8MM_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); > hws[IMX8MM_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); > hws[IMX8MM_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); > diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c > index c5e7316b4c66..e4710d3cf3e0 100644 > --- a/drivers/clk/imx/clk-imx8mn.c > +++ b/drivers/clk/imx/clk-imx8mn.c > @@ -334,7 +334,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) > hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll); > hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll); > hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll); > - hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll); > + hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx_flags("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll_readonly, CLK_GET_RATE_NOCACHE); > hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll); > hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll); > hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll); > diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c > index 030159dc4884..33236d8580a6 100644 > --- a/drivers/clk/imx/clk-pll14xx.c > +++ b/drivers/clk/imx/clk-pll14xx.c > @@ -67,9 +67,8 @@ struct imx_pll14xx_clk imx_1443x_pll = { > .rate_count = ARRAY_SIZE(imx_pll1443x_tbl), > }; > > -struct imx_pll14xx_clk imx_1443x_dram_pll = { > +struct imx_pll14xx_clk imx_1443x_pll_readonly = { > .type = PLL_1443X, > - .flags = CLK_GET_RATE_NOCACHE,
Not really sure what we gain from creating a new function and moving the flag from here to there. I'm personally not fond of it.
Shawn
> }; > > struct imx_pll14xx_clk imx_1416x_pll = { > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index 35a9d294b6df..ea84d2993b57 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -53,7 +53,7 @@ struct imx_pll14xx_clk { > > extern struct imx_pll14xx_clk imx_1416x_pll; > extern struct imx_pll14xx_clk imx_1443x_pll; > -extern struct imx_pll14xx_clk imx_1443x_dram_pll; > +extern struct imx_pll14xx_clk imx_1443x_pll_readonly; > > #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ > to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) > -- > 2.16.4 >
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