Messages in this thread | | | From | Anson Huang <> | Subject | RE: [PATCH] clk: imx: lpcg: write twice when writing lpcg regs | Date | Tue, 10 Sep 2019 02:47:59 +0000 |
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> On Sat, Sep 7, 2019 at 9:47 PM Stephen Boyd <sboyd@kernel.org> wrote: > > > > Quoting Peng Fan (2019-08-27 01:17:50) > > > From: Peng Fan <peng.fan@nxp.com> > > > > > > There is hardware issue that: > > > The output clock the LPCG cell will not turn back on as expected, > > > even though a read of the IPG registers in the LPCG indicates that > > > the clock should be enabled. > > > > > > The software workaround is to write twice to enable the LPCG clock > > > output. > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > > > Does this need a Fixes tag? > > Not sure as it's not code logic issue but a hardware bug. > And 4.19 LTS still have not this driver support.
Looks like there is an errata for this issue, and Ranjani just sent a patch for review internally,
Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by atleast 4 cycles of the gated clock. The workaround is implemented as follows: 1. For clocks running greater than 50MHz no delay is required as the delay in accessing the LPCG register is sufficient. 2. For clocks running greater than 23MHz, a read followed by the write will provide the sufficient delay. 3. For clocks running below 23MHz, LPCG is not used.
Need double check?
Anson.
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