Messages in this thread Patch in this message | | | From | Tony W Wang-oc <> | Subject | [PATCH v1 4/4] x86/mce: Add Zhaoxin LMCE support | Date | Mon, 9 Sep 2019 10:21:32 +0000 |
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Zhaoxin newer CPUs support LMCE that compatible with Intel's "Machine-Check Architecture", so add support for Zhaoxin LMCE in mce/core.c.
Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/core.c | 25 +++++++++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 0986a11..01840ec 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -352,8 +352,10 @@ static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_am #ifdef CONFIG_CPU_SUP_ZHAOXIN void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c); +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c); #else static inline void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) { } +static inline void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) { } #endif #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index a3b07ca..857570f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1129,6 +1129,17 @@ static bool __mc_check_crashing_cpu(int cpu) u64 mcgstatus; mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); + + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { + if (mcgstatus & MCG_STATUS_LMCES) { + return false; + } else { + if (mcgstatus & MCG_STATUS_RIPV) + mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); + return true; + } + } + if (mcgstatus & MCG_STATUS_RIPV) { mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); return true; @@ -1279,9 +1290,10 @@ void do_machine_check(struct pt_regs *regs, long error_code) /* * Check if this MCE is signaled to only this logical processor, - * on Intel only. + * on Intel, Zhaoxin only. */ - if (m.cpuvendor == X86_VENDOR_INTEL) + if (m.cpuvendor == X86_VENDOR_INTEL || + m.cpuvendor == X86_VENDOR_ZHAOXIN) lmce = m.mcgstatus & MCG_STATUS_LMCES; /* @@ -1795,9 +1807,15 @@ void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c) } intel_init_cmci(); + intel_init_lmce(); mce_adjust_timer = cmci_intel_adjust_timer; } +void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) +{ + intel_clear_lmce(); +} + static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { switch (c->x86_vendor) { @@ -1834,6 +1852,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) case X86_VENDOR_INTEL: mce_intel_feature_clear(c); break; + case X86_VENDOR_ZHAOXIN: + mce_zhaoxin_feature_clear(c); + break; default: break; } -- 2.7.4
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