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    SubjectRe: [PATCH v5 6/7] PCI: dwc: al: Add support for DW based driver type
    s/Add support for DW based driver type/Add Amazon Annapurna Labs PCIe controller driver/

    On Thu, Sep 05, 2019 at 05:01:43PM +0300, Jonathan Chocron wrote:
    > This driver is DT based and utilizes the DesignWare APIs.
    >
    > It allows using a smaller ECAM range for a larger bus range -
    > usually an entire bus uses 1MB of address space, but the driver
    > can use it for a larger number of buses. This is achieved by using a HW
    > mechanism which allows changing the BUS part of the "final" outgoing
    > config transaction. There are 2 HW regs, one which is basically a
    > bitmask determining which bits to take from the AXI transaction itself
    > and another which holds the complementary part programmed by the
    > driver.
    >
    > All link initializations are handled by the boot FW.
    >
    > Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
    > Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    > Reviewed-by: Andrew Murray <andrew.murray@arm.com>
    > ---
    > drivers/pci/controller/dwc/Kconfig | 12 +
    > drivers/pci/controller/dwc/pcie-al.c | 365 +++++++++++++++++++++++++++
    > 2 files changed, 377 insertions(+)
    >
    > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
    > index 4fada2e93285..0ba988b5b5bc 100644
    > --- a/drivers/pci/controller/dwc/Kconfig
    > +++ b/drivers/pci/controller/dwc/Kconfig
    > @@ -256,4 +256,16 @@ config PCIE_UNIPHIER
    > Say Y here if you want PCIe controller support on UniPhier SoCs.
    > This driver supports LD20 and PXs3 SoCs.
    >
    > +config PCIE_AL
    > + bool "Amazon Annapurna Labs PCIe controller"
    > + depends on OF && (ARM64 || COMPILE_TEST)
    > + depends on PCI_MSI_IRQ_DOMAIN
    > + select PCIE_DW_HOST
    > + help
    > + Say Y here to enable support of the Amazon's Annapurna Labs PCIe
    > + controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
    > + core plus Annapurna Labs proprietary hardware wrappers. This is
    > + required only for DT-based platforms. ACPI platforms with the
    > + Annapurna Labs PCIe controller don't need to enable this.

    Interesting. How do you deal with the funky ECAM space on ACPI
    platforms? Oh, never mind, I see, it's the pcie-al.c ECAM ops quirk
    that's already in the tree.

    Bjorn

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