Messages in this thread | | | Date | Tue, 03 Sep 2019 11:48:52 -0700 (PDT) | Subject | Re: [PATCH 08/15] riscv: provide native clint access for M-mode | From | Palmer Dabbelt <> |
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On Tue, 27 Aug 2019 23:11:46 PDT (-0700), Christoph Hellwig wrote: > On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote: >> clint0 would be version 0 of the clint, with is the core-local interrupt >> controller in rocket chip. It should be "sifive,clint-1.0.0", not >> "riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of >> legacy device trees floating around, but I'm only considering what's been >> upstream to be actually part of the spec. >> >> In this case the code should match on a "sifive,clint-1.0.0", and the >> device trees should be fixed up to match. We match on "riscv,plic0" for >> legacy systems, and I guess it makes sense to do something similar here. > > IFF we decided to change it I'd rather separate DT noes for the ipi > bank vs timecmp register vs timeval to support variable layouts. The > downside is that we can't just boot on unmodified upstream qemu, which > has used the "riscv,clint0" for years.
Like I alluded to above, matching on "riscv,clint0" seems reasonable to me as it's a defacto standard -- we'll just have to make sure that if we ever end up with a RISC-V CLINT that the DT entry is something else.
As far as splitting the memory maps goes, I don't have a strong opinion but it seems like that'll introduce more complexity than it's worth.
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