Messages in this thread | | | Date | Mon, 23 Sep 2019 11:41:20 +0530 | From | Sibi Sankar <> | Subject | Re: [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register |
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On 2019-09-21 03:50, Stephen Boyd wrote: > Quoting Lina Iyer (2019-09-17 14:50:20) >> On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote: >> >On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote: >> >>Quoting Lina Iyer (2019-09-03 10:07:22) >> >>>On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote: >> >>>>On 02/09/2019 14:38, Rob Herring wrote: >> >>>>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote: >> >>>These are not GIC registers but located on the PDC interface to the GIC. >> >>>They may or may not be secure access controlled, depending on the SoC. >> >>> >> >> >> >>It looks like it falls under this "mailbox" device which is really the >> >>catch all bucket for bits with no home besides they're related to the >> >>apps CPUs/subsystem. >> >> >> >Thanks for pointing to this. >> >> apss_shared: mailbox@17990000 { >> >> compatible = "qcom,sdm845-apss-shared"; >> >> reg = <0 0x17990000 0 0x1000>; >> >But this doesn't seem correct. The registers in this page are all not >> >mailbox door bell registers. We should restrict the space allocated to >> >the mbox to 0xC or something, definitely, not the whole page. They all >> >cannot be treated as a mailbox registers. > > Well the binding is already done and this is the compatible string for > this node and register region. Sounds like this node is a mailbox plus > some more stuff in the same page. >
Bjorn already noticed ^^ during the original review. Hence the compatible was correctly named "apss-shared" instead of following the older bindings.
>> >> #mbox-cells = <1>; >> >> }; >> >> >> >>Can you point to this node with a phandle and then parse the reg >> >>property out of it to use in the scm readl/writel APIs? Maybe it can be >> >>a two cell property with <&apps_shared 0xf0> to indicate the offset to >> >>the registers to read/write? In non-secure mode presumably we need to >> >>also write these registers? Good news is that there's a regmap for this >> >>driver already, so maybe that can be acquired from the pdc driver. >> >> >> >The register space collection seems to be mix of different types of >> >application processor registers that should probably not be grouped up >> >under one subsystem. A single regmap doesn't seem correct either. > > Why isn't a single regmap correct? The PDC driver should be able to use > it to read/write into this register space. The lock on the regmap will > need to be changed to a raw lock though for RT. Otherwise it looks OK > to > me.
-- -- Sibi Sankar -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
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