Messages in this thread | | | From | <> | Subject | Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() | Date | Thu, 19 Sep 2019 15:54:52 +0000 |
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On 09/19/2019 05:33 PM, Vignesh Raghavendra wrote: > Hi Tudor >
Hi, Vignesh,
> [...] > > On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote: >> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new, >> + u8 mask) >> +{ >> + int ret; >> + u8 *sr_cr = nor->bouncebuf; >> + u8 cr_written; >> + >> + /* Make sure we don't overwrite the contents of Status Register 2. */ >> + if (!(nor->flags & SNOR_F_NO_READ_CR)) { > Assuming SNOR_F_NO_READ_CR is not set... > when SNOR_F_NO_READ_CR is not set, I read the Status Register 2 on the next line:
>> + ret = spi_nor_read_cr(nor, &sr_cr[1]); >> + if (ret) >> + return ret; >> + } else if (nor->flash.quad_enable) { >> + /* >> + * If the Status Register 2 Read command (35h) is not >> + * supported, we should at least be sure we don't >> + * change the value of the SR2 Quad Enable bit. >> + * >> + * We can safely assume that when the Quad Enable method is >> + * set, the value of the QE bit is one, as a consequence of the >> + * nor->flash.quad_enable() call. >> + * >> + * We can safely assume that the Quad Enable bit is present in >> + * the Status Register 2 at BIT(1). According to the JESD216 >> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit >> + * Write Status (01h) command is available just for the cases >> + * in which the QE bit is described in SR2 at BIT(1). >> + */
when SNOR_F_NO_READ_CR is set and nor->flash.quad_enable != NULL, Status Register 2 (CR) is equal to CR_QUAD_EN_SPAN.
>> + sr_cr[1] = CR_QUAD_EN_SPAN; >> + } else {
if SNOR_F_NO_READ_CR is set and nor->flash.quad_enable == NULL we don't need to enable Quad Mode, so Status Register 2 is 0.
>> + sr_cr[1] = 0; >> + } >> + > CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code > won't enable quad mode. > >
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