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    Subject[PATCH 4.19 180/190] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
    Date
    [ Upstream commit a8f196a0fa6391a436f63f360a1fb57031fdf26c ]

    On VLV/CHV there is some kind of linkage between the cdclk frequency
    and the DP link frequency. The spec says:
    "For DP audio configuration, cdclk frequency shall be set to
    meet the following requirements:
    DP Link Frequency(MHz) | Cdclk frequency(MHz)
    270 | 320 or higher
    162 | 200 or higher"

    I suspect that would more accurately be expressed as
    "cdclk >= DP link clock", and in any case we can express it like
    that in the code because of the limited set of cdclk (200, 266,
    320, 400 MHz) and link frequencies (162 and 270 MHz) we support.

    Without this we can end up in a situation where the cdclk
    is too low and enabling DP audio will kill the pipe. Happens
    eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
    to pump the pixels (241.5 MHz dotclock) but is too low for
    the DP audio due to the link frequency being 270 MHz.

    v2: Spell out the cdclk and link frequencies we actually support

    Cc: stable@vger.kernel.org
    Tested-by: Stefan Gottwald <gottwald@igel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/20190717114536.22937-1-ville.syrjala@linux.intel.com
    Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
    (cherry picked from commit bffb31f73b29a60ef693842d8744950c2819851d)
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/i915/intel_cdclk.c | 11 +++++++++++
    1 file changed, 11 insertions(+)

    diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
    index 29075c7634280..7b4906ede148b 100644
    --- a/drivers/gpu/drm/i915/intel_cdclk.c
    +++ b/drivers/gpu/drm/i915/intel_cdclk.c
    @@ -2208,6 +2208,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
    if (INTEL_GEN(dev_priv) >= 9)
    min_cdclk = max(2 * 96000, min_cdclk);

    + /*
    + * "For DP audio configuration, cdclk frequency shall be set to
    + * meet the following requirements:
    + * DP Link Frequency(MHz) | Cdclk frequency(MHz)
    + * 270 | 320 or higher
    + * 162 | 200 or higher"
    + */
    + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
    + intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
    + min_cdclk = max(crtc_state->port_clock, min_cdclk);
    +
    /*
    * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
    * than 320000KHz.
    --
    2.20.1


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