Messages in this thread | | | Subject | Re: [PATCH v8 19/21] soc/tegra: pmc: Configure deep sleep control settings | From | Sowjanya Komatineni <> | Date | Fri, 9 Aug 2019 09:23:20 -0700 |
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On 8/9/19 6:23 AM, Dmitry Osipenko wrote: > 09.08.2019 2:46, Sowjanya Komatineni пишет: >> Tegra210 and prior Tegra chips have deep sleep entry and wakeup related >> timings which are platform specific that should be configured before >> entering into deep sleep. >> >> Below are the timing specific configurations for deep sleep entry and >> wakeup. >> - Core rail power-on stabilization timer >> - OSC clock stabilization timer after SOC rail power is stabilized. >> - Core power off time is the minimum wake delay to keep the system >> in deep sleep state irrespective of any quick wake event. >> >> These values depends on the discharge time of regulators and turn OFF >> time of the PMIC to allow the complete system to finish entering into >> deep sleep state. >> >> These values vary based on the platform design and are specified >> through the device tree. >> >> This patch has implementation to configure these timings which are must >> to have for proper deep sleep and wakeup operations. >> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- >> drivers/soc/tegra/pmc.c | 13 ++++++++++++- >> 1 file changed, 12 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c >> index e013ada7e4e9..9a78d8417367 100644 >> --- a/drivers/soc/tegra/pmc.c >> +++ b/drivers/soc/tegra/pmc.c >> @@ -88,6 +88,8 @@ >> >> #define PMC_CPUPWRGOOD_TIMER 0xc8 >> #define PMC_CPUPWROFF_TIMER 0xcc >> +#define PMC_COREPWRGOOD_TIMER 0x3c >> +#define PMC_COREPWROFF_TIMER 0xe0 >> >> #define PMC_PWR_DET_VALUE 0xe4 >> >> @@ -2277,7 +2279,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = { >> >> static void tegra20_pmc_init(struct tegra_pmc *pmc) >> { >> - u32 value; >> + u32 value, osc, pmu, off; >> >> /* Always enable CPU power request */ >> value = tegra_pmc_readl(pmc, PMC_CNTRL); >> @@ -2303,6 +2305,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) >> value = tegra_pmc_readl(pmc, PMC_CNTRL); >> value |= PMC_CNTRL_SYSCLK_OE; >> tegra_pmc_writel(pmc, value, PMC_CNTRL); >> + >> + osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); >> + pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); >> + off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); >> + if (osc && pmu) >> + tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), >> + PMC_COREPWRGOOD_TIMER); >> + if (off) >> + tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); > The osc/pmu/off values are undefined if they are not defined in device-tree. I suppose this > need to be corrected in tegra_pmc_parse_dt() if the values really matter even if LP0 suspend > isn't supported in device-tree. > > And I'm also not sure what's wrong with setting 0 for the timers. > These settings are for SC7 only and will not have any impact in normal state. >> } >> >> static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, >>
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