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    SubjectRe: [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context
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    09.08.2019 2:46, Sowjanya Komatineni пишет:
    > This patch implements save and restore of PLL context.
    >
    > During system suspend, core power goes off and looses the settings
    > of the Tegra CAR controller registers.
    >
    > So during suspend entry pll context is stored and on resume it is
    > restored back along with its state.
    >
    > Acked-by: Thierry Reding <treding@nvidia.com>
    > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
    > ---
    > drivers/clk/tegra/clk-pll.c | 88 ++++++++++++++++++++++++++++-----------------
    > drivers/clk/tegra/clk.h | 2 ++
    > 2 files changed, 58 insertions(+), 32 deletions(-)
    >
    > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
    > index 1583f5fc992f..e52add2bbdbb 100644
    > --- a/drivers/clk/tegra/clk-pll.c
    > +++ b/drivers/clk/tegra/clk-pll.c
    > @@ -1008,6 +1008,28 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
    > return rate;
    > }
    >
    > +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
    > +{
    > + struct tegra_clk_pll *pll = to_clk_pll(hw);
    > + struct clk_hw *parent = clk_hw_get_parent(hw);
    > + unsigned long parent_rate = clk_hw_get_rate(parent);
    > + unsigned long rate = clk_hw_get_rate(hw);
    > + u32 val;
    > +
    > + if (clk_pll_is_enabled(hw))
    > + return;
    > +
    > + if (pll->params->set_defaults)
    > + pll->params->set_defaults(pll);
    > +
    > + clk_pll_set_rate(hw, rate, parent_rate);
    > +
    > + if (!__clk_get_enable_count(hw->clk))

    What about orphaned clocks? Is enable_count > 0 for them?

    > + clk_pll_disable(hw);
    > + else
    > + clk_pll_enable(hw);
    > +}

    [snip]

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