Messages in this thread | | | Subject | Re: [PATCH v1 net-next 4/4] net: stmmac: setup higher frequency clk support for EHL & TGL | From | Florian Fainelli <> | Date | Mon, 26 Aug 2019 12:55:31 -0700 |
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On 8/26/19 6:38 PM, Voon Weifeng wrote: > EHL DW EQOS is running on a 200MHz clock. Setting up stmmac-clk, > ptp clock and ptp_max_adj to 200MHz. > > Signed-off-by: Voon Weifeng <weifeng.voon@intel.com> > Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> > --- > drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 21 +++++++++++++++++++++ > drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c | 3 +++ > include/linux/stmmac.h | 1 + > 3 files changed, 25 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > index e969dc9bb9f0..20906287b6d4 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c > @@ -9,6 +9,7 @@ > Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> > *******************************************************************************/ > > +#include <linux/clk-provider.h> > #include <linux/pci.h> > #include <linux/dmi.h> > > @@ -174,6 +175,19 @@ static int intel_mgbe_common_data(struct pci_dev *pdev, > plat->axi->axi_blen[1] = 8; > plat->axi->axi_blen[2] = 16; > > + plat->ptp_max_adj = plat->clk_ptp_rate; > + > + /* Set system clock */ > + plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, > + "stmmac-clk", NULL, 0, > + plat->clk_ptp_rate); > + > + if (IS_ERR(plat->stmmac_clk)) { > + dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); > + plat->stmmac_clk = NULL;
Don't you need to propagate at least EPROBE_DEFER here? -- Florian
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