Messages in this thread | | | From | Chuanhong Guo <> | Date | Sun, 18 Aug 2019 10:29:29 +0800 | Subject | Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation |
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Hi!
On Sun, Aug 18, 2019 at 2:06 AM Oleksij Rempel <linux@rempel-privat.de> wrote: > >> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks. > >> Jist wild assumption. All peripheral devices are suing bus clock. > > > > This assumption is incorrect. When this patchset is applied in > > OpenWrt, I asked the author why there's still a fixed clock in > > mt7621.dtsi, He told me that there's another clock for those unchanged > > peripherals and he doesn't have time to write a clock provider for it. > > Can you please provide a link to this patch or email.
This discussion is in Chinese and using an IM software so there's no link available.
> We have at least 2 know registers: > SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped > refclock. PLL and dividers used for CPU and some sort of BUS (AHB?). > SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for > all or some ip cores. > What is probably missing is a set of dividers for > each ip core. From your words it is not document.
The specific missing part I was referring to, is parent clocks for every gates. I'm not going to assume this with current openwrt device tree because some peripherals doesn't have a clock binding at all or have a dummy one there.
> > With this information the clk driver will provide gate functionality and > a set of hardcoded clocks. With this driver will work part of power > management and nice devicetree without fixed clocks.
Regards, Chuanhong Guo
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