Messages in this thread | | | From | Chuanhong Guo <> | Date | Sat, 17 Aug 2019 22:42:12 +0800 | Subject | Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation |
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Hi!
On Tue, Aug 13, 2019 at 11:51 PM Rob Herring <robh@kernel.org> wrote: > [...] > > +Example: > > + pll { > > + compatible = "mediatek,mt7621-pll"; > > You didn't answer Stephen's question on v1.
I thought he was asking why there's a syscon in compatible string. I noticed that the syscon in my previous patch is a copy-paste error from elsewhere and dropped it.
> > Based on this binding, there is no way to control/program the PLL. Is > this part of some IP block?
The entire section is called "system control" in datasheet and is occupied in arch/mips/ralink/mt7621.c [0] Two clocks provided here is determined by reading some read-only registers in this part. There's another register in this section providing clock gates for every peripherals, but MTK doesn't provide a clock plan in their datasheet. I can't determine corresponding clock frequencies for every peripherals, thus unable to write a working clock driver.
> > > + > > + #clock-cells = <1>; > > + clock-output-names = "cpu", "bus"; > > + }; > > -- > > 2.21.0 > >
Regards, Chuanhong Guo
[0] https://elixir.bootlin.com/linux/latest/source/arch/mips/ralink/mt7621.c#L156
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