Messages in this thread | | | Subject | Re: [PATCH] clk: imx8mn: fix int pll clk gate | From | Stephen Boyd <> | Date | Fri, 16 Aug 2019 11:02:46 -0700 |
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Quoting peng.fan@nxp.com (2019-08-13 18:53:12) > From: Peng Fan <peng.fan@nxp.com> > > To Frac pll, the gate shift is 13, however to Int PLL the gate shift > is 11. > > Cc: <stable@vger.kernel.org> > Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") > Signed-off-by: Peng Fan <peng.fan@nxp.com> > Reviewed-by: Jacky Bai <ping.bai@nxp.com> > ---
This is a fix for a change in -next. Why is stable Cced?
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