Messages in this thread | | | Date | Fri, 16 Aug 2019 18:31:18 +0100 | From | Will Deacon <> | Subject | Re: [PATCH 6/6] arm64: document the choice of page attributes for pgprot_dmacoherent |
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Hi Christoph,
Thanks for spinning this into a patch.
On Fri, Aug 16, 2019 at 09:07:54AM +0200, Christoph Hellwig wrote: > Based on an email from Will Deacon. > > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/arm64/include/asm/pgtable.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 6700371227d1..6ff221d9a631 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -435,6 +435,14 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) > __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) > #define pgprot_device(prot) \ > __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) > +/* > + * DMA allocations for non-coherent devices use what the Arm architecture calls > + * "Normal non-cacheable" memory, which permits speculation, unaligned accesses > + * and merging of writes. This is different from "Strongly Ordered" memory > + * which is intended for MMIO and thus forbids speculation, preserves access > + * size, requires strict alignment and also forces write responses to come from > + * the endpoint. > + */
Mind if I tweak the second sentence to be:
This is different from "Device-nGnR[nE]" memory which is intended for MMIO and thus forbids speculation, preserves access size, requires strict alignment and can also force write responses to come from the endpoint.
? It's a small change, but it better fits with the arm64 terminology ("strongly ordered" is no longer used in the architecture).
If you're happy with that, I can make the change and queue this patch for 5.4.
Thanks,
Will
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