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    SubjectRe: setup_boot_APIC_clock() NULL dereference during early boot on reduced hardware platforms
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    On 8/1/19 5:13 AM, Thomas Gleixner wrote:
    > On Thu, 1 Aug 2019, Li, Aubrey wrote:
    >> On 2019/8/1 16:13, Thomas Gleixner wrote:
    >>> The point is that it does not matter which vendor a CPU comes from. The
    >>> kernel does support legacyless boot when the frequencies are known. Whether
    >>> that's currently possible on that particular CPU is a different question.
    >>>
    >> Yeah, I should specify, Daniel, your platform needs a global clock event, ;-)
    >
    > Care to look at the manuals before making assumptions?
    >
    > 2.1.9 Timers
    >
    > Each core includes the following timers. These timers do not vary in
    > frequency regardless of the current P-state or C-state.
    >
    > * Core::X86::Msr::TSC; the TSC increments at the rate specified by the
    > P0 Pstate. See Core::X86::Msr::PStateDef.
    >
    > * The APIC timer (Core::X86::Apic::TimerInitialCount and
    > Core::X86::Apic::TimerCurrentCount), which increments at the rate of
    > 2xCLKIN; the APIC timer may increment in units of between 1 and 8.
    >
    > The Ryzens use a 100MHz input clock for the APIC normally, but I'm not sure
    > whether this is subject to overclocking. If so then it should be possible
    > to figure that out somehow. Tom?

    Let me check with the hardware folks and I'll get back to you.

    Thanks,
    Tom

    >
    > Thanks,
    >
    > tglx
    >
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