Messages in this thread | | | From | Richard Zhu <> | Subject | RE: [EXT] Re: [PATCH v3] mailbox: imx: add support for imx v1 mu | Date | Fri, 2 Aug 2019 03:24:16 +0000 |
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> -----Original Message----- > From: Daniel Baluta <daniel.baluta@gmail.com> > Sent: 2019年8月1日 22:47 > To: Richard Zhu <hongxing.zhu@nxp.com> > Cc: jassisinghbrar@gmail.com; Oleksij Rempel <o.rempel@pengutronix.de>; > Aisheng Dong <aisheng.dong@nxp.com>; Linux Kernel Mailing List > <linux-kernel@vger.kernel.org>; linux-arm-kernel > <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com> > Subject: [EXT] Re: [PATCH v3] mailbox: imx: add support for imx v1 mu > > Hi Richard, > > Thanks for the patch. Please always add linux-imx@nxp.com mailing list for imx > related patches. I missed it. > [Richard Zhu] Okay, roger that.
> Few comments inline. > > Please also update in a separate patch attached to this series the devictree > bindings doc Documentation/devicetree/bindings/mailbox/fsl,mu.txt > by adding description for mx7ulp-mu > > <snip> [Richard Zhu] Okay, the binding doc would be added later. > > > There is a version1.0 MU on i.MX7ULP platform. > > space between version and 1.0 > [Richard Zhu] Okay.
> > One new version ID register is added, and it's offset is 0. > > TRn registers are defined at the offset 0x20 ~ 0x2C. > > RRn registers are defined at the offset 0x40 ~ 0x4C. > > SR/CR registers are defined at 0x60/0x64. > > Extend this driver to support it. > > Do you have a little bit of history about MU versioning? So there was: > > * version 0.5 on i.MX6-es > * version 1.0 on i.MX7ULP > > Next, is this 1.0 compatbile with i.MX8 right? > [Richard Zhu] Only i.MX7ULP has the version 1.0 MU. i.MX8 has the same version MU that i.MX6-es have. IMHO, I don't know why design team do it this way.
> Also, can you please rebase your patch on my 2 bugfixes attached? [Richard Zhu] Okay, no problem. I would send the v4 version out later after rebase your 2 bugfixes patches. > > thanks, > Daniel.
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