Messages in this thread | | | From | "Ghannam, Yazen" <> | Subject | [PATCH v2 0/7] AMD64 EDAC fixes | Date | Tue, 9 Jul 2019 21:56:54 +0000 |
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From: Yazen Ghannam <yazen.ghannam@amd.com>
Hi Boris,
This set contains a few fixes for some changes merged in v5.2. There are also a couple of fixes for older issues. In addition, there are a couple of patches to add support for Asymmetric Dual-Rank DIMMs.
Thanks, Yazen
Link: https://lkml.kernel.org/r/20190531234501.32826-1-Yazen.Ghannam@amd.com
v1->v2: * Squash patches 1 and 2 together.
Yazen Ghannam (7): EDAC/amd64: Support more than two controllers for chip selects handling EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP EDAC/amd64: Initialize DIMM info for systems with more than two channels EDAC/amd64: Find Chip Select memory size using Address Mask EDAC/amd64: Decode syndrome before translating address EDAC/amd64: Cache secondary Chip Select registers EDAC/amd64: Support Asymmetric Dual-Rank DIMMs
drivers/edac/amd64_edac.c | 348 ++++++++++++++++++++++++-------------- drivers/edac/amd64_edac.h | 9 +- 2 files changed, 232 insertions(+), 125 deletions(-)
-- 2.17.1
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