Messages in this thread | | | From | Jon Masters <> | Date | Mon, 8 Jul 2019 20:25:52 -0400 | Subject | Re: [PATCH 0/2] arm64: Introduce boot parameter to disable TLB flush instruction within the same inner shareable domain |
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On 7/2/19 10:45 PM, qi.fuli@fujitsu.com wrote:
> However, we found that with the increase of that the TLB flash was called, > the noise was also increasing. Here we understood that the cause of this > issue is the implementation of Linux's TLB flush for arm64, especially use of > TLBI-is instruction which is a broadcast to all processor core on the system.
Are you saying that for a microbenchmark in which very large numbers of threads are created and destroyed rapidly there are a large number of associated tlb range flushes which always use broadcast TLBIs?
If that's the case, and the hardware doesn't do any ASID filtering and each TLBI results in a DVM to every PE, would it make sense to look at whether there are ways to improve batching/switch to an IPI approach rather than relying on broadcasts, as a more generic solution?
Jon.
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