Messages in this thread | | | Subject | Re: [RFC PATCH 06/16] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls | From | Paolo Bonzini <> | Date | Tue, 30 Jul 2019 11:35:54 +0200 |
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On 30/07/19 10:43, Paolo Bonzini wrote: > On 29/07/19 13:56, Anup Patel wrote: >> The PC register represents program counter whereas the MODE >> register represent VCPU privilege mode (i.e. S/U-mode). >> > Is there any reason to include this pseudo-register instead of allowing > SSTATUS access directly in this patch (and perhaps also SEPC)?
Nevermind, I was confused - the current MODE is indeed not accessible as a "real" CSR in RISC-V.
Still, I would prefer all the VS CSRs to be accessible via the get/set reg ioctls.
Paolo
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