Messages in this thread | | | Subject | Re: [RESEND][PATCH] clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1 | From | Stephen Boyd <> | Date | Mon, 22 Jul 2019 14:32:14 -0700 |
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Quoting Codrin Ciubotariu (2019-06-25 02:10:02) > In clk_generated_determine_rate(), if the divisor is greater than > GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned. > If clk_generated_set_rate() will be called later with this wrong > rate, it will return -EINVAL, so the generated clock won't change > its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1. > > Fixes: 8c7aa6328947 ("clk: at91: clk-generated: remove useless divisor loop") > Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> > Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> > Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> > ---
Applied to clk-fixes
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