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    Subject[PATCH AUTOSEL 4.14 054/105] x86/atomic: Fix smp_mb__{before,after}_atomic()
    Date
    From: Peter Zijlstra <peterz@infradead.org>

    [ Upstream commit 69d927bba39517d0980462efc051875b7f4db185 ]

    Recent probing at the Linux Kernel Memory Model uncovered a
    'surprise'. Strongly ordered architectures where the atomic RmW
    primitive implies full memory ordering and
    smp_mb__{before,after}_atomic() are a simple barrier() (such as x86)
    fail for:

    *x = 1;
    atomic_inc(u);
    smp_mb__after_atomic();
    r0 = *y;

    Because, while the atomic_inc() implies memory order, it
    (surprisingly) does not provide a compiler barrier. This then allows
    the compiler to re-order like so:

    atomic_inc(u);
    *x = 1;
    smp_mb__after_atomic();
    r0 = *y;

    Which the CPU is then allowed to re-order (under TSO rules) like:

    atomic_inc(u);
    r0 = *y;
    *x = 1;

    And this very much was not intended. Therefore strengthen the atomic
    RmW ops to include a compiler barrier.

    NOTE: atomic_{or,and,xor} and the bitops already had the compiler
    barrier.

    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    Documentation/atomic_t.txt | 3 +++
    arch/x86/include/asm/atomic.h | 8 ++++----
    arch/x86/include/asm/atomic64_64.h | 8 ++++----
    arch/x86/include/asm/barrier.h | 4 ++--
    4 files changed, 13 insertions(+), 10 deletions(-)

    diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt
    index 913396ac5824..ed0d814df7e0 100644
    --- a/Documentation/atomic_t.txt
    +++ b/Documentation/atomic_t.txt
    @@ -177,6 +177,9 @@ These helper barriers exist because architectures have varying implicit
    ordering on their SMP atomic primitives. For example our TSO architectures
    provide full ordered atomics and these barriers are no-ops.

    +NOTE: when the atomic RmW ops are fully ordered, they should also imply a
    +compiler barrier.
    +
    Thus:

    atomic_fetch_add();
    diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
    index 72759f131cc5..d09dd91dd0b6 100644
    --- a/arch/x86/include/asm/atomic.h
    +++ b/arch/x86/include/asm/atomic.h
    @@ -50,7 +50,7 @@ static __always_inline void atomic_add(int i, atomic_t *v)
    {
    asm volatile(LOCK_PREFIX "addl %1,%0"
    : "+m" (v->counter)
    - : "ir" (i));
    + : "ir" (i) : "memory");
    }

    /**
    @@ -64,7 +64,7 @@ static __always_inline void atomic_sub(int i, atomic_t *v)
    {
    asm volatile(LOCK_PREFIX "subl %1,%0"
    : "+m" (v->counter)
    - : "ir" (i));
    + : "ir" (i) : "memory");
    }

    /**
    @@ -90,7 +90,7 @@ static __always_inline bool atomic_sub_and_test(int i, atomic_t *v)
    static __always_inline void atomic_inc(atomic_t *v)
    {
    asm volatile(LOCK_PREFIX "incl %0"
    - : "+m" (v->counter));
    + : "+m" (v->counter) :: "memory");
    }

    /**
    @@ -102,7 +102,7 @@ static __always_inline void atomic_inc(atomic_t *v)
    static __always_inline void atomic_dec(atomic_t *v)
    {
    asm volatile(LOCK_PREFIX "decl %0"
    - : "+m" (v->counter));
    + : "+m" (v->counter) :: "memory");
    }

    /**
    diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
    index 738495caf05f..e6fad6bbb2ee 100644
    --- a/arch/x86/include/asm/atomic64_64.h
    +++ b/arch/x86/include/asm/atomic64_64.h
    @@ -45,7 +45,7 @@ static __always_inline void atomic64_add(long i, atomic64_t *v)
    {
    asm volatile(LOCK_PREFIX "addq %1,%0"
    : "=m" (v->counter)
    - : "er" (i), "m" (v->counter));
    + : "er" (i), "m" (v->counter) : "memory");
    }

    /**
    @@ -59,7 +59,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
    {
    asm volatile(LOCK_PREFIX "subq %1,%0"
    : "=m" (v->counter)
    - : "er" (i), "m" (v->counter));
    + : "er" (i), "m" (v->counter) : "memory");
    }

    /**
    @@ -86,7 +86,7 @@ static __always_inline void atomic64_inc(atomic64_t *v)
    {
    asm volatile(LOCK_PREFIX "incq %0"
    : "=m" (v->counter)
    - : "m" (v->counter));
    + : "m" (v->counter) : "memory");
    }

    /**
    @@ -99,7 +99,7 @@ static __always_inline void atomic64_dec(atomic64_t *v)
    {
    asm volatile(LOCK_PREFIX "decq %0"
    : "=m" (v->counter)
    - : "m" (v->counter));
    + : "m" (v->counter) : "memory");
    }

    /**
    diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h
    index a04f0c242a28..bc88797cfa61 100644
    --- a/arch/x86/include/asm/barrier.h
    +++ b/arch/x86/include/asm/barrier.h
    @@ -106,8 +106,8 @@ do { \
    #endif

    /* Atomic operations are already serializing on x86 */
    -#define __smp_mb__before_atomic() barrier()
    -#define __smp_mb__after_atomic() barrier()
    +#define __smp_mb__before_atomic() do { } while (0)
    +#define __smp_mb__after_atomic() do { } while (0)

    #include <asm-generic/barrier.h>

    --
    2.20.1
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