Messages in this thread | | | Date | Tue, 4 Jun 2019 13:45:15 +0100 | From | Catalin Marinas <> | Subject | Re: [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size |
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On Tue, May 28, 2019 at 10:16:53AM +0800, Shaokun Zhang wrote: > Add coherency_max_size variable to record the maximum cache line size > for different cache levels. If it is available, we will synchronize > it as cache line size, otherwise we will use CTR_EL0.CWG reporting > in cache_line_size() for arm64. > > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> > Cc: "Rafael J. Wysocki" <rafael@kernel.org> > Cc: Sudeep Holla <sudeep.holla@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Jeremy Linton <jeremy.linton@arm.com> > Cc: Will Deacon <will.deacon@arm.com> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Both patches queued for 5.3. Thanks.
-- Catalin
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