Messages in this thread Patch in this message | | | From | Anson.Huang@nxp ... | Subject | [PATCH RESEND 2/2] clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m | Date | Wed, 26 Jun 2019 09:28:03 +0800 |
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From: Anson Huang <Anson.Huang@nxp.com>
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m, NOT sys_pll1_800m, correct it.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx8mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 516e68d..d1a84f7 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -293,7 +293,7 @@ static const char *imx8mm_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_1 "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", }; static const char *imx8mm_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", "sys_pll1_40m", - "video_pll1_out", "sys_pll1_800m", "audio_pll1_out", "clk_ext1" }; + "video_pll1_out", "sys_pll1_80m", "audio_pll1_out", "clk_ext1" }; static const char *imx8mm_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; -- 2.7.4
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