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    Subject[PATCH 4.19 097/118] PCI: rcar: Fix 64bit MSI message address handling
    Date
    [ Upstream commit 954b4b752a4c4e963b017ed8cef4c453c5ed308d ]

    The MSI message address in the RC address space can be 64 bit. The
    R-Car PCIe RC supports such a 64bit MSI message address as well.
    The code currently uses virt_to_phys(__get_free_pages()) to obtain
    a reserved page for the MSI message address, and the return value
    of which can be a 64 bit physical address on 64 bit system.

    However, the driver only programs PCIEMSIALR register with the bottom
    32 bits of the virt_to_phys(__get_free_pages()) return value and does
    not program the top 32 bits into PCIEMSIAUR, but rather programs the
    PCIEMSIAUR register with 0x0. This worked fine on older 32 bit R-Car
    SoCs, however may fail on new 64 bit R-Car SoCs.

    Since from a PCIe controller perspective, an inbound MSI is a memory
    write to a special address (in case of this controller, defined by
    the value in PCIEMSIAUR:PCIEMSIALR), which triggers an interrupt, but
    never hits the DRAM _and_ because allocation of an MSI by a PCIe card
    driver obtains the MSI message address by reading PCIEMSIAUR:PCIEMSIALR
    in rcar_msi_setup_irqs(), incorrectly programmed PCIEMSIAUR cannot
    cause memory corruption or other issues.

    There is however the possibility that if virt_to_phys(__get_free_pages())
    returned address above the 32bit boundary _and_ PCIEMSIAUR was programmed
    to 0x0 _and_ if the system had physical RAM at the address matching the
    value of PCIEMSIALR, a PCIe card driver could allocate a buffer with a
    physical address matching the value of PCIEMSIALR and a remote write to
    such a buffer by a PCIe card would trigger a spurious MSI.

    Fixes: e015f88c368d ("PCI: rcar: Add support for R-Car H3 to pcie-rcar")
    Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
    Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Cc: Geert Uytterhoeven <geert+renesas@glider.be>
    Cc: Phil Edworthy <phil.edworthy@renesas.com>
    Cc: Simon Horman <horms+renesas@verge.net.au>
    Cc: Wolfram Sang <wsa@the-dreams.de>
    Cc: linux-renesas-soc@vger.kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pci/controller/pcie-rcar.c | 6 +++---
    1 file changed, 3 insertions(+), 3 deletions(-)

    diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
    index 765c39911c0c..9b9c677ad3a0 100644
    --- a/drivers/pci/controller/pcie-rcar.c
    +++ b/drivers/pci/controller/pcie-rcar.c
    @@ -892,7 +892,7 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
    {
    struct device *dev = pcie->dev;
    struct rcar_msi *msi = &pcie->msi;
    - unsigned long base;
    + phys_addr_t base;
    int err, i;

    mutex_init(&msi->lock);
    @@ -937,8 +937,8 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
    }
    base = virt_to_phys((void *)msi->pages);

    - rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
    - rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
    + rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
    + rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);

    /* enable all MSI interrupts */
    rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
    --
    2.20.1


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