Messages in this thread | | | Subject | Re: [PATCH 5/6] iommu/vt-d: Cleanup after delegating DMA domain to generic iommu | From | Lu Baolu <> | Date | Tue, 11 Jun 2019 13:43:41 +0800 |
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Hi,
On 6/11/19 3:25 AM, Sai Praneeth Prakhya wrote: > On Mon, 2019-06-10 at 11:45 -0700, Mehta, Sohil wrote: >> On Sun, 2019-06-09 at 10:38 +0800, Lu Baolu wrote: >>> static int __init si_domain_init(int hw) >>> @@ -3306,14 +3252,13 @@ static int __init init_dmars(void) >>> if (pasid_supported(iommu)) >>> intel_svm_init(iommu); >>> #endif >>> - } >>> >>> - /* >>> - * Now that qi is enabled on all iommus, set the root entry >>> and flush >>> - * caches. This is required on some Intel X58 chipsets, >>> otherwise the >>> - * flush_context function will loop forever and the boot >>> hangs. >>> - */ >>> - for_each_active_iommu(iommu, drhd) { >>> + /* >>> + * Now that qi is enabled on all iommus, set the root >>> entry and >>> + * flush caches. This is required on some Intel X58 >>> chipsets, >>> + * otherwise the flush_context function will loop >>> forever and >>> + * the boot hangs. >>> + */ >>> iommu_flush_write_buffer(iommu); >>> iommu_set_root_entry(iommu); >>> iommu->flush.flush_context(iommu, 0, 0, 0, >>> DMA_CCMD_GLOBAL_INVL); >> >> This changes the intent of the original code. As the comment says >> enable QI on all IOMMUs, then flush the caches and set the root entry. >> The order of setting the root entries has changed now. >> >> Refer: >> Commit a4c34ff1c029 ('iommu/vt-d: Enable QI on all IOMMUs before >> setting root entry') > > Thanks Sohil! for catching the bug. > Will send a V2 to Lu Baolu fixing this.
Okay, I will submit a v2 of this series later.
> > Regards, > Sai
Best regards, Baolu
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