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    Subject[PATCH v3 4/5] ARM: dts: r7s72100: Add IRQC device node
    Date
    Enable support for the IRQC on RZ/A1H, which is a small front-end to the
    GIC. This allows to use up to 8 external interrupts with configurable
    sense select.

    Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
    ---
    v3:
    - Use interrupt-map (+ #address-cells and interrupt-map-mask) instead
    of renesas,gic-spi-base,

    v2:
    - Add Reviewed-by,
    - Add "renesas,gic-spi-base".
    ---
    arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
    1 file changed, 19 insertions(+)

    diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
    index 2211f88ede2ad351..d03dcd919d6f5cfb 100644
    --- a/arch/arm/boot/dts/r7s72100.dtsi
    +++ b/arch/arm/boot/dts/r7s72100.dtsi
    @@ -670,6 +670,25 @@
    status = "disabled";
    };

    + irqc: interrupt-controller@fcfef800 {
    + compatible = "renesas,r7s72100-irqc",
    + "renesas,rza1-irqc";
    + #interrupt-cells = <2>;
    + #address-cells = <0>;
    + interrupt-controller;
    + reg = <0xfcfef800 0x6>;
    + interrupt-map =
    + <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
    + <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
    + <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
    + <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
    + <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
    + <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
    + <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
    + <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-map-mask = <7 0>;
    + };
    +
    mtu2: timer@fcff0000 {
    compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
    reg = <0xfcff0000 0x400>;
    --
    2.17.1
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