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    SubjectRe: [PATCH 10/12] pinctrl: sunxi: Support I/O bias voltage setting on H6
    On Sat, Apr 06, 2019 at 01:45:12AM +0200, megous@megous.com wrote:
    > From: Ondrej Jirman <megous@megous.com>
    >
    > H6 SoC has a "pio group withstand voltage mode" register (datasheet
    > description), that needs to be used to select either 1.8V or 3.3V
    > I/O mode, based on what voltage is powering the respective pin
    > banks and is thus used for I/O signals.
    >
    > Add support for configuring this register according to the voltage
    > of the pin bank regulator (if enabled).
    >
    > This is similar to the support for I/O bias voltage setting patch
    > for A80 and the same concerns apply. (see commit 402bfb3c135213dc
    > Support I/O bias voltage setting on A80).
    >
    > Signed-off-by: Ondrej Jirman <megous@megous.com>
    > ---
    > drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 +
    > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 ++++++++++++++
    > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
    > 3 files changed, 18 insertions(+)
    >
    > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
    > index ef4268cc6227..30b1befa8ed8 100644
    > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
    > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
    > @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
    > .irq_banks = 4,
    > .irq_bank_map = h6_irq_bank_map,
    > .irq_read_needs_mux = true,
    > + .io_bias_cfg_variant = IO_BIAS_CFG_V2,
    > };
    >
    > static int h6_pinctrl_probe(struct platform_device *pdev)
    > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
    > index 9f329fec77cf..59a4ed396d92 100644
    > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
    > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
    > @@ -607,6 +607,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
    > unsigned pin,
    > struct regulator *supply)
    > {
    > + unsigned short bank = pin / PINS_PER_BANK;
    > + unsigned long flags;
    > u32 val, reg;
    > int uV;
    >
    > @@ -639,6 +641,18 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
    > reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
    > reg &= ~IO_BIAS_MASK;
    > writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
    > + } else if (pctl->desc->io_bias_cfg_variant == IO_BIAS_CFG_V2) {
    > + val = uV <= 1800000 ? 1 : 0;
    > +
    > + dev_info(pctl->dev,
    > + "Setting voltage bias to %sV on bank P%c\n",
    > + val ? "1.8" : "3.3", 'A' + bank);
    > +
    > + raw_spin_lock_irqsave(&pctl->lock, flags);
    > + reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
    > + reg &= ~(1 << bank);
    > + writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
    > + raw_spin_unlock_irqrestore(&pctl->lock, flags);
    > }
    >
    > return 0;
    > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
    > index 476772f91dba..3a66376f141b 100644
    > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
    > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
    > @@ -95,7 +95,10 @@
    > #define PINCTRL_SUN7I_A20 BIT(7)
    > #define PINCTRL_SUN8I_R40 BIT(8)
    >
    > +#define PIO_POW_MOD_SEL_REG 0x340
    > +
    > #define IO_BIAS_CFG_V1 1
    > +#define IO_BIAS_CFG_V2 2

    Can you document what V1 and V2 means exactly?

    Thanks!
    Maxime

    --
    Maxime Ripard, Bootlin
    Embedded Linux and Kernel engineering
    https://bootlin.com
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