Messages in this thread | | | Date | Tue, 9 Apr 2019 11:02:31 +0800 | From | Guo Ren <> | Subject | Re: [PATCH v2] RISC-V: Implement ASID allocator |
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Hi Anup,
On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote: > This patch is tested on QEMU/virt machine and SiFive Unleashed board. > On QEMU/virt machine, we see 10% (approx) performance improvement with > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP CSR > are not implemented on SiFive Unleashed board so we don't see any change > in performance. Can you tell me what is the test case ?
Best Regards Guo Ren
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