Messages in this thread Patch in this message | | | From | Biao Huang <> | Subject | [PATCH 2/4] net: stmmac: fix csr_clk can't be zero issue | Date | Mon, 29 Apr 2019 14:15:54 +0800 |
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The specific clk_csr value can be zero, and stmmac_clk is necessary for MDC clock which can be set dynamically. So, change the condition from plat->clk_csr to plat->stmmac_clk to fix clk_csr can't be zero issue.
Signed-off-by: Biao Huang <biao.huang@mediatek.com> --- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 818ad88..9e89b94 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -4376,7 +4376,7 @@ int stmmac_dvr_probe(struct device *device, * set the MDC clock dynamically according to the csr actual * clock input. */ - if (!priv->plat->clk_csr) + if (priv->plat->stmmac_clk) stmmac_clk_csr_set(priv); else priv->clk_csr = priv->plat->clk_csr; -- 1.7.9.5
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