Messages in this thread | | | Date | Sat, 27 Apr 2019 02:45:04 +0300 | From | Serge Semin <> | Subject | Re: [PATCH v2 1/2] net: phy: realtek: Add rtl8211e rx/tx delays config |
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On Fri, Apr 26, 2019 at 11:40:50PM +0200, Andrew Lunn wrote: > On Sat, Apr 27, 2019 at 12:21:11AM +0300, Serge Semin wrote: > > There are two chip pins named TXDLY and RXDLY which actually adds the 2ns > > delays to TXC and RXC for TXD/RXD latching. Alas this is the only > > documented info regarding the RGMII timing control configurations the PHY > > provides. It turns out the same settings can be setup via MDIO registers > > hidden in the extension pages layout. Particularly the extension page 0xa4 > > provides a register 0x1c, which bits 1 and 2 control the described delays. > > They are used to implement the "rgmii-{id,rxid,txid}" phy-mode. > > > > The hidden RGMII configs register utilization was found in the rtl8211e > > U-boot driver: > > https://elixir.bootlin.com/u-boot/v2019.01/source/drivers/net/phy/realtek.c#L99 > > > > There is also a freebsd-folks discussion regarding this register: > > https://reviews.freebsd.org/D13591 > > > > It confirms that the register bits field must control the so called > > configuration pins described in the table 12-13 of the official PHY > > datasheet: > > 8:6 = PHY Address > > 5:4 = Auto-Negotiation > > 3 = Interface Mode Select > > 2 = RX Delay > > 1 = TX Delay > > 0 = SELRGV > > > > Signed-off-by: Serge Semin <fancer.lancer@gmail.com> > > > Hi Serge > > Next time please include a patch 0 containing a cover note explaining > the who series. >
Sure as long as the patchset gets to be much bigger than two small patches with an obvious reason to be merged.
> Reviewed-by: Andrew Lunn <andrew@lunn.ch> >
Thanks.)
-Sergey
> Andrew
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