Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v1 1/2] clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider | Date | Thu, 25 Apr 2019 08:17:32 -0700 |
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Quoting Dmitry Osipenko (2019-04-11 14:48:34) > There are wrongly set parenthesis in the code that are resulting in a > wrong configuration being programmed for PLLM. The original fix was made > by Danny Huang in the downstream kernel. The patch was tested on Nyan Big > Tegra124 chromebook, PLLM rate changing works correctly now and system > doesn't lock up after changing the PLLM rate due to EMC scaling. > > Cc: <stable@vger.kernel.org> > Tested-by: Steev Klimaszewski <steev@kali.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > ---
Applied to clk-next
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