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    Subject[PATCH V8 4/5] drm/mediatek: no change parent rate in round_rate() for mt2701 hdmi phy
    Date
    From: Wangyan Wang <wangyan.wang@mediatek.com>

    This is the third step to make MT2701 HDMI stable.
    We should not change the rate of parent for hdmi phy when
    doing round_rate for this clock. The parent clock of hdmi
    phy must be the same as it. We change it when doing set_rate
    only.

    Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com>
    ---
    drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 14 --------------
    drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 2 --
    drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 6 ++++++
    drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++++++++++++++
    4 files changed, 20 insertions(+), 16 deletions(-)

    diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    index 13bbaf997819..fe05aa762107 100644
    --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    @@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
    .owner = THIS_MODULE,
    };

    -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    - unsigned long *parent_rate)
    -{
    - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
    -
    - hdmi_phy->pll_rate = rate;
    - if (rate <= 74250000)
    - *parent_rate = rate;
    - else
    - *parent_rate = rate / 2;
    -
    - return rate;
    -}
    -
    unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
    unsigned long parent_rate)
    {
    diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    index 0045824c1be9..86895be0d192 100644
    --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    @@ -49,8 +49,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    u32 val, u32 mask);
    struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
    -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    - unsigned long *parent_rate);
    unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
    unsigned long parent_rate);

    diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    index 844e622f052c..5f8c2b044034 100644
    --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    @@ -154,6 +154,12 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
    return 0;
    }

    +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    + unsigned long *parent_rate)
    +{
    + return rate;
    +}
    +
    static const struct clk_ops mtk_hdmi_phy_pll_ops = {
    .prepare = mtk_hdmi_pll_prepare,
    .unprepare = mtk_hdmi_pll_unprepare,
    diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    index f44066875dcd..472d2fda0a03 100644
    --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    @@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
    return 0;
    }

    +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    + unsigned long *parent_rate)
    +{
    + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
    +
    + hdmi_phy->pll_rate = rate;
    + if (rate <= 74250000)
    + *parent_rate = rate;
    + else
    + *parent_rate = rate / 2;
    +
    + return rate;
    +}
    +
    static const struct clk_ops mtk_hdmi_phy_pll_ops = {
    .prepare = mtk_hdmi_pll_prepare,
    .unprepare = mtk_hdmi_pll_unprepare,
    --
    2.14.1
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