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    Subject[PATCH v20 06/28] x86/mm: x86/sgx: Add new 'PF_SGX' page fault error code bit
    Date
    From: Sean Christopherson <sean.j.christopherson@intel.com>

    The SGX bit is set in the #PF error code if and only if the fault is
    detected by the Enclave Page Cache Map (EPCM), a hardware-managed
    table that enforces the paging permissions defined by the enclave,
    e.g. to prevent the kernel from changing the permissions of an
    enclave's page(s).

    Despite triggering a #PF, a #PF with PF_SGX has nothing to do with
    paging.

    Cc: Dave Hansen <dave.hansen@linux.intel.com>
    Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
    Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
    ---
    arch/x86/include/asm/traps.h | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
    index 7d6f3f3fad78..c3e02912e9c7 100644
    --- a/arch/x86/include/asm/traps.h
    +++ b/arch/x86/include/asm/traps.h
    @@ -171,5 +171,6 @@ enum x86_pf_error_code {
    X86_PF_RSVD = 1 << 3,
    X86_PF_INSTR = 1 << 4,
    X86_PF_PK = 1 << 5,
    + X86_PF_SGX = 1 << 15,
    };
    #endif /* _ASM_X86_TRAPS_H */
    --
    2.19.1
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