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    Subject[tip:x86/fpu] x86/entry: Add TIF_NEED_FPU_LOAD
    Commit-ID:  383c252545edcc708128e2028a2318b05c45ede4
    Gitweb: https://git.kernel.org/tip/383c252545edcc708128e2028a2318b05c45ede4
    Author: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    AuthorDate: Wed, 3 Apr 2019 18:41:45 +0200
    Committer: Borislav Petkov <bp@suse.de>
    CommitDate: Thu, 11 Apr 2019 16:21:51 +0200

    x86/entry: Add TIF_NEED_FPU_LOAD

    Add TIF_NEED_FPU_LOAD. This flag is used for loading the FPU registers
    before returning to userland. It must not be set on systems without a
    FPU.

    If this flag is cleared, the CPU's FPU registers hold the latest,
    up-to-date content of the current task's (current()) FPU registers.
    The in-memory copy (union fpregs_state) is not valid.

    If this flag is set, then all of CPU's FPU registers may hold a random
    value (except for PKRU) and it is required to load the content of the
    FPU registers on return to userland.

    Introduce it now as a preparatory change before adding the main feature.

    Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Dave Hansen <dave.hansen@intel.com>
    Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
    Cc: Andy Lutomirski <luto@kernel.org>
    Cc: Aubrey Li <aubrey.li@intel.com>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Jann Horn <jannh@google.com>
    Cc: "Jason A. Donenfeld" <Jason@zx2c4.com>
    Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
    Cc: kvm ML <kvm@vger.kernel.org>
    Cc: Paolo Bonzini <pbonzini@redhat.com>
    Cc: Radim Krčmář <rkrcmar@redhat.com>
    Cc: Rik van Riel <riel@surriel.com>
    Cc: Tim Chen <tim.c.chen@linux.intel.com>
    Cc: x86-ml <x86@kernel.org>
    Link: https://lkml.kernel.org/r/20190403164156.19645-17-bigeasy@linutronix.de
    ---
    arch/x86/include/asm/fpu/internal.h | 8 ++++++++
    arch/x86/include/asm/thread_info.h | 2 ++
    2 files changed, 10 insertions(+)

    diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h
    index 6eb4a0b1ad0e..da75d7b3e37d 100644
    --- a/arch/x86/include/asm/fpu/internal.h
    +++ b/arch/x86/include/asm/fpu/internal.h
    @@ -508,6 +508,14 @@ static inline void __fpregs_load_activate(struct fpu *fpu, int cpu)
    * - switch_fpu_finish() restores the new state as
    * necessary.
    *
    + * If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
    + * are saved in the current thread's FPU register state.
    + *
    + * If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
    + * hold current()'s FPU registers. It is required to load the
    + * registers before returning to userland or using the content
    + * otherwise.
    + *
    * The FPU context is only stored/restored for a user task and
    * ->mm is used to distinguish between kernel and user threads.
    */
    diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
    index e0eccbcb8447..f9453536f9bb 100644
    --- a/arch/x86/include/asm/thread_info.h
    +++ b/arch/x86/include/asm/thread_info.h
    @@ -88,6 +88,7 @@ struct thread_info {
    #define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */
    #define TIF_UPROBE 12 /* breakpointed or singlestepping */
    #define TIF_PATCH_PENDING 13 /* pending live patching update */
    +#define TIF_NEED_FPU_LOAD 14 /* load FPU on return to userspace */
    #define TIF_NOCPUID 15 /* CPUID is not accessible in userland */
    #define TIF_NOTSC 16 /* TSC is not accessible in userland */
    #define TIF_IA32 17 /* IA32 compatibility process */
    @@ -117,6 +118,7 @@ struct thread_info {
    #define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
    #define _TIF_UPROBE (1 << TIF_UPROBE)
    #define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING)
    +#define _TIF_NEED_FPU_LOAD (1 << TIF_NEED_FPU_LOAD)
    #define _TIF_NOCPUID (1 << TIF_NOCPUID)
    #define _TIF_NOTSC (1 << TIF_NOTSC)
    #define _TIF_IA32 (1 << TIF_IA32)
    \
     
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