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    Subject[PATCH V7 6/6] drm/mediatek: fix the rate of parent for hdmi phy in MT2701
    Date
    From: chunhui dai <chunhui.dai@mediatek.com>

    We should not change the rate of parent for hdmi phy when
    doing round_rate for this clock. The parent clock of hdmi
    phy must be the same as it. We change it when doing set_rate
    only.

    Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
    Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
    ---
    drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 19 -------------------
    drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 4 ----
    drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 7 +++++++
    drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++++++++++++++
    4 files changed, 21 insertions(+), 23 deletions(-)

    diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    index 370309d684ec..f753ee72971e 100644
    --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
    @@ -15,25 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
    .owner = THIS_MODULE,
    };

    -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    - unsigned long *parent_rate)
    -{
    - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
    -
    - hdmi_phy->pll_rate = rate;
    - if (rate <= 74250000)
    - *parent_rate = rate;
    - else
    - *parent_rate = rate / 2;
    -
    - return rate;
    -}
    -
    -u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset)
    -{
    - return readl(hdmi_phy->regs + offset);
    -}
    -
    void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    u32 bits)
    {
    diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    index 446e2acd1926..4d4de4de8977 100644
    --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
    @@ -42,7 +42,6 @@ struct mtk_hdmi_phy {
    unsigned int ibias_up;
    };

    -u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset);
    void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    u32 bits);
    void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    @@ -50,9 +49,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
    u32 val, u32 mask);
    struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
    -long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    - unsigned long *parent_rate);
    -
    extern struct platform_driver mtk_hdmi_phy_driver;
    extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
    extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
    diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    index cb0c68c94013..6fb4ca943463 100644
    --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
    @@ -152,6 +152,13 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
    RG_HDMITX_DRV_IBIAS_MASK);
    return 0;
    }
    +
    +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    + unsigned long *parent_rate)
    +{
    + return rate;
    +}
    +
    static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
    unsigned long parent_rate)
    {
    diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    index 63dde42521b8..3a339f516613 100644
    --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
    @@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
    return 0;
    }

    +static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
    + unsigned long *parent_rate)
    +{
    + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
    +
    + hdmi_phy->pll_rate = rate;
    + if (rate <= 74250000)
    + *parent_rate = rate;
    + else
    + *parent_rate = rate / 2;
    +
    + return rate;
    +}
    +
    static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
    unsigned long parent_rate)
    {
    --
    2.14.1
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