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    Subject[PATCH v19,RESEND 03/27] x86/msr: Add IA32_FEATURE_CONTROL.SGX_ENABLE definition
    Date
    From: Sean Christopherson <sean.j.christopherson@intel.com>

    Add a new IA32_FEATURE_CONTROL bit, SGX_ENABLE, which must be set in
    order to execute SGX instructions, i.e. ENCL{S,U,V}. The existence of
    the bit is enumerated by CPUID as X86_FEATURE_SGX. Like all other
    flags in IA32_FEATURE_CONTROL, the MSR must be locked for SGX_ENABLE
    to take effect.

    Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
    Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
    ---
    arch/x86/include/asm/msr-index.h | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
    index ca5bc0eacb95..6efaa8026c64 100644
    --- a/arch/x86/include/asm/msr-index.h
    +++ b/arch/x86/include/asm/msr-index.h
    @@ -525,6 +525,7 @@
    #define FEATURE_CONTROL_LOCKED (1<<0)
    #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
    #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
    +#define FEATURE_CONTROL_SGX_ENABLE (1<<18)
    #define FEATURE_CONTROL_LMCE (1<<20)

    #define MSR_IA32_APICBASE 0x0000001b
    --
    2.19.1
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