Messages in this thread Patch in this message | | | From | Alistair Francis <> | Subject | [PATCH] irqchip: plic: Fix priority base offset | Date | Wed, 20 Mar 2019 22:39:52 +0000 |
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According to the FU540 and E31 manuals the PLIC source priority address starts at an offset of 0x04 and not 0x00. To aviod confusion update the address and source offset to match the documentation. This causes no difference in functionality.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- drivers/irqchip/irq-sifive-plic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index cf755964f2f8..826e7293d608 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -35,7 +35,7 @@ * Each interrupt source has a priority register associated with it. * We always hardwire it to one in Linux. */ -#define PRIORITY_BASE 0 +#define PRIORITY_BASE 0x04 #define PRIORITY_PER_ID 4 /* @@ -88,7 +88,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask, { int cpu; - writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); + writel(enable, plic_regs + PRIORITY_BASE + (hwirq - 1) * PRIORITY_PER_ID); for_each_cpu(cpu, mask) { struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); -- 2.21.0
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