Messages in this thread | | | Date | Sun, 17 Mar 2019 11:42:08 +0100 | From | Neil Armstrong <> | Subject | Re: [PATCH 6/9] arm64: dts: meson: g12a: Add UART A, B & C nodes and pins |
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Le 16/03/2019 23:14, Martin Blumenstingl a écrit : > Hi Neil, > > On Sat, Mar 16, 2019 at 3:35 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > [...] >>>> + uart_ao_a_c_pins: uart_ao_a_c { >>>> + mux { >>>> + groups = "uart_ao_a_rx_c", >>>> + "uart_ao_a_tx_c"; >>>> + function = "uart_ao_a_c"; >>>> + bias-disable; >>>> + }; >>>> + }; >>> I'm fine with this part if you mention it in the subject and/or the description >>> uart_ao_a_c routes two pins from bank C (from the EE domain) to the >>> uart_AO controller (from the AO domain) >> >> Not sure DT is the right place for that, I think I'll remove this until >> we have it actually used somewhere. > I'm fine with that as well > > [...] >>>> + >>>> + uart_C: serial@22000 { >>>> + compatible = "amlogic,meson-gx-uart"; >>>> + reg = <0x0 0x22000 0x0 0x18>; >>>> + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; >>>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; >>> does uart_C really use CLKID_UART1? on GX uart_C uses CLKID_UART2 >> >> It seems so : >> https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L1020 > it's weird but we can always fix it up later if needed. so let's keep > it for now to stay consistent with the vendor kernel until we know > better > > Jianxin, can you please check with the hardware team whether the > uart_C gate clock (pclk) is CLKID_UART1 or CLKID_UART2 on G12A?
I think it's a typo, it should use CLKID_UART2
Neil
> > > Regards > Martin >
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