Messages in this thread | | | From | Rob Herring <> | Date | Thu, 14 Mar 2019 15:14:24 -0500 | Subject | Re: [PATCH v2 1/8] drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support |
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On Thu, Mar 14, 2019 at 3:07 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > Hi Rob, > > Le 14/03/2019 19:55, Rob Herring a écrit : > > On Mon, Mar 11, 2019 at 3:53 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > >> > >> On 08/03/2019 15:54, Rob Herring wrote: > >>> On Fri, Mar 8, 2019 at 2:05 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > >>>> > >>>> Hi Rob, > >>>> > >>>> On 08/03/2019 00:13, Rob Herring wrote: > >>>>> On Fri, Feb 1, 2019 at 6:08 AM Neil Armstrong <narmstrong@baylibre.com> wrote: > >>>>>> > >>>>>> Add support for SCDC Setup for TMDS Clock > 3.4GHz and enable TMDS > >>>>>> Scrambling when supported or mandatory. > >>>>>> > >>>>>> This patch also adds an helper to setup the control bit to support > >>>>>> the high TMDS Bit Period/TMDS Clock-Period Ratio as required with > >>>>>> TMDS Clock > 3.4GHz for HDMI2.0 3840x2160@60/50 modes. > >>>>>> > >>>>>> These changes were based on work done by Huicong Xu <xhc@rock-chips.com> > >>>>>> and Nickey Yang <nickey.yang@rock-chips.com> to support HDMI2.0 modes > >>>>>> on the Rockchip 4.4 BSP kernel at [1] > >>>>>> > >>>>>> [1] https://github.com/rockchip-linux/kernel/tree/release-4.4 > >>>>>> > >>>>>> Cc: Nickey Yang <nickey.yang@rock-chips.com> > >>>>>> Cc: Huicong Xu <xhc@rock-chips.com> > >>>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > >>>>>> Tested-by: Heiko Stuebner <heiko@sntech.de> > >>>>>> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> > >>>>>> --- > >>>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 85 ++++++++++++++++++++++++++++++- > >>>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + > >>>>>> include/drm/bridge/dw_hdmi.h | 1 + > >>>>>> 3 files changed, 85 insertions(+), 2 deletions(-) > >>>>> > >>>>> This commit in drm-misc-next is breaking booting on the Rock960. I > >>>>> have FB and fbcon enabled. The boot hangs after this message: > >>>>> > >>>>> [ 3.012334] [drm:rockchip_drm_fbdev_create] FB [1920x1080]-24 > >>>>> kvaddr=(____ptrval____) offset=0 size=8294400 > >>>> > >>>> Could you give more details on the tree used ? did you bisect to find this commit ? > >>> > >>> As I said above, drm-misc-next (from drm-misc tree) is the branch. I > >>> bisected between it and v5.0. Reverting it fixes booting. > >> > >> Thanks, could you give more details on the environment ? Did you test over the latest linux-next ? > > > > Here's a log of the drm parts: https://pastebin.com/tFJ9Gs6h > > > > linux-next also hangs. > > > >> Can you share the EDID of your monitor ? > > > > Maybe not mode related. I tried forcing to 1280x720 and it hangs too. > > In any case, here's the parsed EDID: > > > > 256-byte EDID successfully retrieved from i2c bus 3 > > Looks like i2c was successful. Have a good day. > > Checksum Correct > > > > Section "Monitor" > > Identifier "CYS-R101" > > ModelName "CYS-R101" > > VendorName "CYX" > > # Monitor Manufactured week 28 of 2018 > > # EDID version 1.3 > > # Digital Display > > DisplaySize 220 130 > > Gamma 2.20 > > Option "DPMS" "true" > > Horizsync 30-102 > > VertRefresh 48-75 > > # Maximum pixel clock is 190MHz > > #Not giving standard mode: 1920x1080, 60Hz > > #Not giving standard mode: 1920x1080, 60Hz > > #Not giving standard mode: 1920x1080, 60Hz > > #Not giving standard mode: 1440x900, 60Hz > > #Not giving standard mode: 1400x1050, 60Hz > > #Not giving standard mode: 1280x1024, 60Hz > > #Not giving standard mode: 1280x960, 60Hz > > #Not giving standard mode: 1280x720, 60Hz > > > > #Extension block found. Parsing... > > Modeline "Mode 5" 54.00 2560 2608 2640 2720 1440 1443 1448 1481 +hsync +vsync > > Modeline "Mode 0" 267.81 2560 2608 2640 2720 1600 1603 1608 1641 +hsync +vsync > > Modeline "Mode 1" 148.500 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync > > Modeline "Mode 2" 74.250 1920 2008 2052 2200 1080 1082 1087 1125 > > +hsync +vsync interlace > > Modeline "Mode 3" 74.250 1280 1390 1420 1650 720 725 730 750 +hsync +vsync > > Modeline "Mode 4" 148.500 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync > > Option "PreferredMode" "Mode 5" > > EndSection > > > >> Can you check this patch : > > > > Still hangs with it. > > > Thanks for testing, the only impact would be if hdmi_info->scdc.supported > and hdmi_info->scdc.scrambling.low_rate were true. > Honestly, hdmi_info->scdc.scrambling.low_rate wasn't really tested. > > Could you dump the edid in binary format ? or parse it with https://github.com/rpavlik/edid-decode > supporting modern HDMI EDIDs.
Here's with edid-decode:
EDID version: 1.3 Manufacturer: CYX Model 101 Serial Number 16843009 Made in week 28 of 2018 Digital display Maximum image size: 22 cm x 13 cm Gamma: 2.20 DPMS levels: Off Undefined display color type Default (sRGB) color space is primary color space First detailed timing is preferred timing Display x,y Chromaticity: Red: 0.6455, 0.3300 Green: 0.3095, 0.6171 Blue: 0.1523, 0.0732 White: 0.3134, 0.3291 Established timings supported: 640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz 800x600@60Hz 4:3 HorFreq: 37900 Hz Clock: 40.000 MHz 1024x768@60Hz 4:3 HorFreq: 48400 Hz Clock: 65.000 MHz Standard timings supported: 1920x1080@60Hz 16:9 1920x1080@60Hz 16:9 1920x1080@60Hz 16:9 1440x900@60Hz 16:10 HorFreq: 55500 Hz Clock: 88.750 MHz 1400x1050@60Hz 4:3 HorFreq: 64700 Hz Clock: 101.000 MHz 1280x1024@60Hz 5:4 HorFreq: 64000 Hz Clock: 108.000 MHz 1280x960@60Hz 4:3 HorFreq: 60000 Hz Clock: 108.000 MHz 1280x720@60Hz 16:9 Detailed mode: Clock 267.810 MHz, 220 mm x 130 mm 2560 2608 2640 2720 hborder 0 1600 1603 1608 1641 vborder 0 +hsync +vsync VertFreq: 59 Hz, HorFreq: 98459 Hz Monitor name: CYS-R101 Serial number: Monitor ranges (bare limits): 48-75Hz V, 30-102kHz H, max dotclock 190MHz Has 1 extension blocks Checksum: 0x8b (valid)
CTA extension block Extension version: 3 58 bytes of CTA data Video data block VIC 16 1920x1080@60Hz 16:9 HorFreq: 67500 Hz Clock: 148.500 MHz VIC 5 1920x1080i@60Hz 16:9 HorFreq: 33750 Hz Clock: 74.250 MHz VIC 4 1280x720@60Hz 16:9 HorFreq: 45000 Hz Clock: 74.250 MHz VIC 31 1920x1080@50Hz 16:9 HorFreq: 56250 Hz Clock: 148.500 MHz Audio data block Linear PCM, max channels 2 Supported sample rates (kHz): 48 44.1 32 Supported sample sizes (bits): 24 20 16 Speaker allocation data block Speaker map: FL/FR - Front Left/Right Vendor-specific data block, OUI 000c03 (HDMI) Source physical address 1.0.0.0 DC_36bit DC_30bit DC_Y444 Maximum TMDS clock: 340MHz Vendor-specific data block, OUI c45dd8 (HDMI Forum) Version: 1 Maximum TMDS Character Rate: 340MHz SCDC Present Supports 10-bits/component Deep Color 4:2:0 Pixel Encoding Vendor-specific data block, OUI 00001a Extended tag: YCbCr 4:2:0 capability map data block VSD Index 17 VSD Index 18 Extended tag: Colorimetry data block BT2020YCC BT2020RGB Extended tag: Video capability data block YCbCr quantization: Selectable (via AVI YQ) (1) RGB quantization: Selectable (via AVI Q) (1) PT scan behaviour: Support both over- and underscan (3) IT scan behaviour: Support both over- and underscan (3) CE scan behaviour: Support both over- and underscan (3) Extended tag: HDR static metadata data block Electro optical transfer functions: Traditional gamma - SDR luminance range SMPTE ST2084 Supported static metadata descriptors: Static metadata type 1 Desired content max luminance: 89 (343.724 cd/m^2) Desired content max frame-average luminance: 89 (343.724 cd/m^2) Desired content min luminance: 73 (0.282 cd/m^2) Underscans PC formats by default Basic audio support Supports YCbCr 4:4:4 Supports YCbCr 4:2:2 1 native detailed modes Detailed mode: Clock 54.000 MHz, 220 mm x 130 mm 2560 2608 2640 2720 hborder 0 1440 1443 1448 1481 vborder 0 +hsync +vsync side by side interleaved VertFreq: 13 Hz, HorFreq: 19852 Hz Checksum: 0x3c (valid)
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