Messages in this thread | | | Date | Thu, 14 Mar 2019 16:46:28 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset |
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On Thu, Mar 14, 2019 at 07:21:08PM +0800, Icenowy Zheng wrote: > The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8. > > Fix this problem. > > Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Applied, thanks! Maxime
-- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com [unhandled content-type:application/pgp-signature] | |