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    Subject[PATCH v2 04/10] dt-bindings: mailbox: Add a sunxi message box binding
    Date
    This mailbox hardware is present in Allwinner sun8i, sun9i, and sun50i
    SoCs. Add a device tree binding for it.

    Signed-off-by: Samuel Holland <samuel@sholland.org>
    ---
    .../bindings/mailbox/sunxi-msgbox.txt | 44 +++++++++++++++++++
    1 file changed, 44 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt

    diff --git a/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt b/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
    new file mode 100644
    index 000000000000..4560ab8efeca
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/mailbox/sunxi-msgbox.txt
    @@ -0,0 +1,44 @@
    +Allwinner sun6i Message Box
    +===========================
    +
    +The hardware message box on sun6i and newer sunxi SoCs is a two-user mailbox
    +controller containing 8 unidirectional FIFOs. An interrupt is raised for
    +received messages, but software must poll to know when a transmitted message has
    +been acknowledged by the remote user.
    +
    +Refer to ./mailbox.txt for generic information about mailbox device-tree
    +bindings.
    +
    +Mailbox Device Node:
    +====================
    +
    +Required properties:
    +--------------------
    +- compatible: Must contain at least "allwinner,sun6i-a31-msgbox".
    + Should also contain another SoC-specific string when
    + used on other SoCs which are compatible, e.g.
    + - allwinner,sun6i-a31-msgbox
    + - allwinner,sun8i-a83t-msgbox, allwinner,sun6i-a31-msgbox
    + - allwinner,sun8i-h3-msgbox, allwinner,sun6i-a31-msgbox
    + - allwinner,sun9i-a80-msgbox, allwinner,sun6i-a31-msgbox
    + - allwinner,sun50i-a64-msgbox, allwinner,sun6i-a31-msgbox
    + - allwinner,sun50i-h6-msgbox, allwinner,sun6i-a31-msgbox
    +- reg: Contains the mailbox register address range (base
    + address and length).
    +- clocks: phandle for the bus clock controller and specifier.
    +- resets: phandle for the bus reset controller and specifier.
    +- interrupts: Contains interrupt information for the mailbox.
    +- #mbox-cells: Must be 1.
    +
    +Example:
    +--------
    +
    + msgbox: mailbox@1c17000 {
    + compatible = "allwinner,sun8i-h3-msgbox",
    + "allwinner,sun6i-a31-msgbox";
    + reg = <0x01c17000 0x1000>;
    + clocks = <&ccu CLK_BUS_MSGBOX>;
    + resets = <&ccu RST_BUS_MSGBOX>;
    + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
    + #mbox-cells = <1>;
    + };
    --
    2.19.2
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